Semiconductor integrated circuit including command decoder for receiving control signals

ABSTRACT

A delay circuit and a plurality of accepting circuits are comprised. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is adjusted to optimize an accepting timing to an input signal by a clock signal in each of the accepting circuit. The each accepting circuit reliably accepts the delayed input signal respectively in synchronization with a clock signal. Therefore, it is unnecessary to respectively provide a delay circuit in the plurality of the accepting circuits. As a result, the plurality of accepting circuits can reliably accept input signals without enlarging a circuit scale. A plurality of delay circuits, a plurality of accepting circuits, and an operating circuit are comprised. The delay circuit receives a plurality of input signals, and outputs each of the delayed input signals respectively to the plurality of accepting circuits. The accepting circuit accepts the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of the each delay circuit, for example, is in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor integratedcircuits, and more particularly to a semiconductor integrated circuitwhich operates so as to accept input signals in synchronization with aclock signal.

[0003] 2. Description of the Related Art

[0004] In general, semiconductor integrated circuits are broadlyclassified into logic LSIs, such as a microcomputer, and memory LSIs,such as a DRAM. The microcomputer has been widely known as asemiconductor integrated circuit which operates in synchronization witha clock. On the other hand, in the memory LSIs, an SDRAM (SynchronousDRAM) or the like operating in synchronization with a clock has beendeveloped.

[0005] In the SDRAM, an interfacing circuit is operated at high speed insynchronization with a clock signal supplied from exterior, so thatwriting or reading data at high speed is made possible while timingmargins are kept.

[0006]FIG. 1 shows the block diagram of an input interfacing circuit 1in the semiconductor integrated circuit of this kind. The inputinterfacing circuit 1 includes a clock buffer 2, a plurality of inputbuffers 3 a, 3 b, 3 c, and a plurality of input signal acceptingcircuits 4 a, 6 4 b, 4 c. Each of the input signal accepting circuits 4a, 4 b, 4 cincludes a latch 5. The clock buffer 2 is supplied with aclock signal CLK from exterior of a chip. This clock buffer 2 decidesthe signal level of the clock signal CLK, converts the clock signal CLKinto an internal clock signal CLKIN of high level or low level, andoutputs the internal clock signal CLKIN to the respective input signalaccepting circuits 4 a, 4 b, 4 c. The input buffers 3 a, 3 b, 3 c arerespectively supplied with input signals S1, S2, S3 from exterior of thechip. These input buffers 3 a, 3 b, 3 c decide the signal levels of theinput signals S1, S2, S3, convert the input signals S1, S2, S3 intointernal signals SIN1, SIN2, SIN3 of high level or low level, and outputthe internal signals SIN1, SIN2, SIN3 to the input signal acceptingcircuits 4 a, 4 b, 4 c, respectively. The latches 5 accept the internalsignals SIN1, SIN2, SIN3 in synchronization with the edge of theinternal clock signal CLKIN, and output accepted signals SIN1A, SIN2A,SIN3A to a controlling circuit 6, or the like. within the chip,respectively. In the figure, lines indicated by arrows denote wiringpatterns, and the directions of the arrows denote the directions inwhich the signals are transmitted.

[0007] In the input interfacing circuit 1 described above, ordinarilythe input buffers 3 a, 3 b, 3 c are arranged near pads for receiving thesignals from exterior and are dispersed on the chip. In contrast, theinput signal accepting circuits 4 a, 4 b, 4 c are arranged at thepredetermined position on the chip. Therefore, the wiring patterns whichare respectively laid to transmit the internal signals SIN1, SIN2, SIN3between the input buffers 3 a, 3 b, 3 c and the input signal acceptingcircuits 4 a, 4 b, 4 c can not have the same lengths. By way of example,the wiring pattern for transmitting the internal signal SIN1 is theshortest, and the wiring pattern for transmitting the internal signalSIN3 is the longest. Since the propagation delay time of each signal isproportional to the length of the wiring pattern, the internal signalsSIN1, SIN2, SIN3 are respectively supplied to the input signal acceptingcircuits 4 a, 4 b, 4 c at timings different from one another.

[0008] As a result, the timings of the respective latches 5 foraccepting the internal signals SIN1, SIN2, SIN3 shift as shown in FIG.2. In the example of FIG. 2, the signal in which a timing margin for aset-up time tS is the smallest is the internal signal SIN3, and thesignal in which a timing margin for a hold time tH is the smallest isthe internal signal SIN1. Here, the “set-up time tS” is thespecification of the minimum time in which the input signal needs to besettled before the rise of the clock signal CLK, and the “hold time tH”is the specification of the minimum time in which the input signal needsto be held after the rise of the clock signal CLK. Besides, in general,the ratings of external input terminals for the set-up time tS and thehold time tH are specified by the worst value of all input signals. Forthis reason, when the accepting timings of the internal signals SIN1,SIN2, SIN3 fluctuates, the timing margins of the external inputterminals for the set-up time tS and the hold time tH become short.

[0009] The specifications of the set-up time tS and the hold time tHneed to be strictened more as the frequency of the clock signal CLKbecomes higher. In the SDRAM of high speed operation, therefore, theinput signal accepting circuits 4 a, 4 b, 4 c are respectively furnishedwith delay circuits 7 a, 7 b, 7 c on the input sides of the latches 5 asshown in FIG. 3, thereby to lower the fluctuation of the timings of theinternal signals SIN1, SIN2, SIN3. In the figure, the sizes of the delaycircuits 7 a, 7 b, 7 c express the lengths of delay times. The delaycircuits 7 a, 7 b, 7 c are respectively adjusted in accordance with thedelays of the internal signals SIN1, SIN2, SIN3 attributed to theunequal lengths of the wiring patterns, and the timings at which theinternal signals SIN1, SIN2, SIN3 are respectively transmitted to thelatches 5 are set same. In consequence, the set-up times tS and holdtimes tH of all the internal signals SIN1, SIN2, SIN3 are equalized.

[0010] Meanwhile, in an SDRAM or the like, the combinations of thesignal levels of a plurality of input signals received insynchronization with a clock signal CLK are decided as a plurality ofcontrolling commands, by which an internal circuit is controlled.

[0011] As shown in FIG. 4, the input interfacing unit 1 of the SDRAM ofthis type is formed with a decoder 8 which receives accepted signalsSIN1A, SIN2A, SIN3A output from respective latches 5, and which outputsa command signal CMD.

[0012] With the circuit shown in FIG. 4, the output of the commandsignal CMD delays because the internal signals SIN1A, SIN2A, SIN3Aaccepted by the corresponding latches 5 are decoded by the decoder 8. Asa result, the operation of a controlling circuit 6 delays, and an accesstime, or the like. cannot be enhanced. In order to quicken the output ofthe command signal CMD, internal signals SIN1, SIN2, SIN3 before beingaccepted by the latches 5 should be decoded.

[0013] Each of FIGS. 5 and 6 shows the construction of the principalparts of an input interfacing unit 1 which serves to decode the internalsignals SIN1, SIN2, SIN3 before being accepted by the latches 5, andwhich has been thought out by the inventor of the present invention.

[0014] The input interfacing unit 1 shown in FIG. 5 is formed with acommand accepting unit 9 which includes a decoder 10, a delay circuit 7d and a latch circuit 5. The decoder 10 receives the internal signalsSIN1, SIN2, SIN3, and outputs a command signal CMD to the delay circuit7 d. The delay circuit 7 d outputs the delayed command signal to thelatch circuit 5. The latch circuit 5 accepts the delayed command signalCMD in synchronization with an internal clock signal CLKIN, and outputsthe accepted signal to the controlling circuit 6 as a command signalCMD1. Here, the delay circuit 7 d is a circuit for adjusting the timingsof the command signal CMD and the internal clock signal CLKIN which aresupplied to the latch circuit 5.

[0015] The input interfacing unit 1 shown in FIG. 6 is formed with acommand accepting unit 11 which includes delay circuits 7 e, 7 f, 7 g, adecoder 10 and a latch circuit 5. The decoder 10 receives the internalsignals SIN1, SIN2, SIN3 through the delay circuits 7 e, 7 f, 7 g,respectively, and outputs a command signal CMD to the latch circuit 5.The latch circuit 5 accepts the command signal CMD in synchronizationwith an internal clock signal CLKIN, and outputs the accepted signal tothe controlling circuit 6 as a command signal CMD1.

[0016] It is added that the input interfacing units 1 shown in FIGS. 5and 6 are not known yet.

[0017] With the input interfacing unit 1 shown in FIG. 5, the commandsignal CMD has its width W narrowed by the decoder 10 as shown in FIG.7. This incurs the problem that the timing margins of the command signalCMD for the set-up time tS and the hold time tH become small in thelatch circuit 5.

[0018] On the other hand, with the circuit construction shown in FIG. 6,the command latch 11 is formed with the plurality of delay circuits 7 e,7 f, 7 g. The input interfacing unit 1 requires delay circuits foradjusting the timings of the respective latches for the input signals,besides the delay circuits 7 e, 7 f, 7 g. This results in the problemthat the number of the delay circuits increases to enlarge the circuitscale. The enlargement of the circuit scale leads to that of a chipsize. Since the enlargement of the chip size directly affects productioncosts, it exerts serious influence especially on the memory LSI such asDRAM.

SUMMARY OF THE INVENTION

[0019] An object of the present invention is to provide a semiconductorintegrated circuit which can reliably receive input signals withoutenlarging the circuit scale.

[0020] Another object of the present invention is to provide asemiconductor integrated circuit where an internal circuit can bequickly and reliably operated.

[0021] Still another object of the present invention is to set anoptimal delay time of an input signal.

[0022] According to one of the aspects of the semiconductor integratedcircuit in the present invention, the semiconductor integrated circuitcomprises a delay circuit and a plurality of receiver circuits. Theinput signal supplied from exterior is delayed for a predeterminedlength of time by the delay circuit, and then it is distributed andoutput to the plurality of the receiver circuits. The delay time of thedelay circuit is set so that a receiving timing of an input signalreceived in synchronization with a clock signal is optimized in each ofthe receiver circuits. Each receiver circuit reliably receives thedelayed input signal respectively in synchronization with a clocksignal.

[0023] Therefore, it is unnecessary to provide a delay circuit in eachof the plurality of receiver circuits. As a result, the plurality ofreceiver circuits can reliably receive the input signals withoutenlarging the circuit scale. When there is a need to adjust the delaytime of the input signals, only one of the delay circuits needs to bechanged.

[0024] Generally, in the semiconductor integrated circuit, the delaycircuit is constructed by combining a resistor and a capacitor whosesizes are designed according to the lengths and the sizes of wirings,diffusion layers and insulators. This often results in the enlargementof the layout size of a delay circuit as compared to other circuits. Thepresent invention makes it possible to reduce the number of the delaycircuits so that the size of each delay circuit can be also be reducedas well as the size of the chip.

[0025] According to another aspect of the semiconductor integratedcircuit in the present invention, switching the ON/OFF state of a switchprovided in the delay circuit enables the transmission path of the inputsignal to change and its delay time to be adjusted. Therefore, when itis necessary to adjust the delay time of the input signal, only theswitch needs to be changed.

[0026] According to another aspect of the semiconductor integratedcircuit in the present invention, the semiconductor integrated circuitcomprises a plurality of delay circuits, a plurality of receivercircuits, and an operating circuit. The delay circuit receives aplurality of input signals, and respectively outputs each of the delayedinput signals to the plurality of receiver circuits. The receivercircuit receives the delayed input signals in synchronization with aclock signal. More than one of the delayed input signals are supplied tothe operating circuit to perform a logic operation. The delay time ofeach delay circuit, for example, is set in accordance with the supplyingtiming to the input signal supplied to the operating circuit. As aresult, the operating circuit performs the logic operation with asufficient timing margin, and the timing margin between the inputsignals supplied to the operating circuit does not fluctuate, even whenthe delay time of each delay circuit is relatively shifted. Byrelatively shifting the delay time of each delay circuit, each receivercircuit becomes capable of reliably receiving the delayed input signalrespectively in synchronization with a clock signal. Consequently, thedelay circuit is able to supply input signals to both the operatingcircuit and the receiver circuit at an optimal timing.

[0027] According to another aspect of the semiconductor integratedcircuit in the present invention, the logical operating circuit isconstructed as a command decoder and it comprises a command signalreceiver circuit, which receives a command signal output from thecommand decoder in synchronization with a clock signal.

[0028] The command decoder directly receives the input signals delayedby the delay circuits and outputs a command signal controlling theoperations of internal circuits. The command signal receiver circuitreliably receives a wide command signal output from the command decoderin synchronization with a clock signal. Since the command signalreceiver circuit receives the command signal decoded by the commanddecoder, an early start can be made in the operations of the internalcircuits. Besides, there can be a plurality of command decoders andthere can be a common delay circuit between the command decoders, sothat the number of the delay circuits is further reduced to also reducethe size of each delay circuit as well as the size of the chip.

[0029] According to another aspect of the semiconductor integratedcircuit in the present invention, switching the ON/OFF state of theswitch enables the transmission path of the input signal to change andits delay time to be adjusted. Therefore, the optimal delay time of theeach delay circuit can be set. When it is necessary to adjust the delaytime of the input signal, only the switch needs to be changed. Thelayout data of the elements of the delay circuit other than the switchis made common between each other, so that the layout designing time maybe shortened.

[0030] The delay time of the each delay circuit is adjusted so that thesupply timings to the command decoder are equal between each inputsignal. This prevents the pulse width of the command decoder frombecoming narrower so that the internal circuits can be reliablyoperated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The nature, principle, and utility of the invention will becomemore apparent from the following detailed description when read inconjunction with the accompanying drawings in which like parts aredesignated by identical reference numbers, in which:

[0032]FIG. 1 is a block diagram showing the construction of an inputinterfacing unit in the prior art semiconductor integrated circuit;

[0033]FIG. 2 is a timing chart showing the timings at which internalsignals are accepted in the prior art;

[0034]FIG. 3 is a block diagram showing the construction of anotherinput interfacing unit in the prior art semiconductor integratedcircuit;

[0035]FIG. 4 is a block diagram showing the construction of an inputinterfacing unit in the prior art semiconductor integrated circuitincluding a command decoder;

[0036]FIG. 5 is a block diagram showing the construction of theprincipal parts of an input interfacing unit thought out by the inventorof the present invention;

[0037]FIG. 6 is a block diagram showing the construction of theprincipal parts of another input interfacing unit thought out by theinventor;

[0038]FIG. 7 is a timing chart showing the timing at which a decodedsignal is accepted in the input interfacing unit shown in FIG. 5;

[0039]FIG. 8 is a block diagram showing the basic principles of thefirst embodiment of a semiconductor integrated circuit according to thepresent invention;

[0040]FIG. 9 is a block diagram showing the first embodiment of asemiconductor integrated circuit according to the present invention;

[0041]FIG. 10 is a block diagram showing the construction of theprincipal parts of an input interfacing unit in FIG. 9;

[0042]FIG. 11 is a circuit diagram showing the details of a clock bufferin FIG. 10;

[0043]FIG. 12 is a circuit diagram showing the details of each of inputbuffers in FIG. 10;

[0044]FIG. 13 is a circuit diagram showing the details of delay circuitsin FIG. 10;

[0045]FIG. 14 is a circuit diagram showing the details of each oflatches and a command latch in FIG. 10;

[0046]FIG. 15 is a circuit diagram showing the details of a commanddecoder in FIG. 10;

[0047]FIG. 16 is a timing chart showing the decoding timings of internalsignals and the accepting timing of a decoded signal; and

[0048]FIG. 17 is a block diagram showing the second embodiment of thesemiconductor integrated circuit according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Now, the embodiments of the present invention will be describedwith reference to the drawings.

[0050]FIG. 8 is a block diagram showing the basic principles of thefirst embodiment of a semiconductor integrated circuit according to thepresent invention.

[0051] The semiconductor integrated circuit includes a plurality ofdelay circuits 39 each having switches S, and a plurality of receivercircuits 41, 43. A plurality of input signals IN1, IN2 supplied fromexterior are delayed predetermined time periods by each delay circuit39, and the delayed signals are distributed and output toward theplurality of accepting circuits 41, 43. The transmission path of each ofthe input signals IN1, IN2 is altered by changing the ON/OFF states ofthe switches S included in each delay circuit 39, whereby the delay timeis adjusted.

[0052] Besides, the receiver circuit 43 includes a logic operatingcircuit 45 and a command signal receiver circuit 46. The delayed inputsignals IN1, IN2 (in general, numbering two or more) are supplied to thelogical operating circuit 45 so as to perform a logic operation. In thisexample, the logical operating circuit 45 is constructed as a commanddecoder. The command decoder 45 directly receives the input signals IN1,IN2 delayed by the delay circuits 39, and outputs a command signal CMDfor controlling the operations of internal circuits 23, 25. The commandsignal receiver circuit 46 receives the command signal CMD output fromthe command decoder 45, in synchronization with a clock signal CLK.

[0053]FIG. 9 shows the first embodiment of the semiconductor integratedcircuit according to the present invention.

[0054] The semiconductor integrated circuit of this embodiment is formedon a silicon substrate as an SDRAM by using CMOS process technology.

[0055] The SDRAM includes an input interfacing unit 21, a controllingunit 23 and two memory core units 25. The input interfacing unit 21 isconfigured of input units 27 arranged as two divided portions, and anaccepting unit 29 arranged substantially in the center of a chip. Thecontrolling unit 23 and the memory core units 25 correspond to theinternal circuits (23, 25 in FIG. 8). Each of the input units 27includes a plurality of pads 31 (which correspond to pads 31 a, 31 b, 31c, 31 d to be mentioned below), and a plurality of input circuits 33(which correspond to input circuits 33 a, 33 b, 33 c, 33 d to bementioned below). In FIG. 9, lines indicated by arrows denote wiringpatterns, and the senses of the arrows denote the directions in whichsignals are transmitted.

[0056]FIG. 10 is a block diagram showing the construction of theprincipal parts of the input interfacing unit 21. In the figure, onlythree major input signals are illustrated.

[0057] Each of the input units 27 is formed with the pads 31 a, 31 b, 31c and 31 d which receive a clock signal CLK, a chip select signal ICS, arow address strobe signal/RAS and a column address strobe signal /CASfrom exterior, respectively. The pads 31 a, 31 b, 31 c, 31 d arerespectively connected to the corresponding input circuits 33 a, 33 b,33 c, 33 d. The input circuit 33 a includes a clock buffer 35. The clockbuffer 35 decides the signal level of the clock signal CLK suppliedthrough the pad 31 a, converts the clock signal CLK into an internalclock signal CLKIN of high level or low level, and outputs the internalclock signal CLKIN to the accepting unit 29.

[0058] The input circuit 33 b includes an input buffer 37 and a delaycircuit 39 a. Likewise, the input circuit 33 c includes an input buffer37 and a delay circuit 39 b. Also, the input circuit 33 d includes aninput buffer 37 and a delay circuit 39 c.

[0059] The input buffer 37 of the input circuit 33 b decides the signallevel of the chip select signal /CS supplied through the pad 31 b,converts the chip select signal /CS into an internal signal CSX of highlevel or low level, and outputs the internal signal CSX to the delaycircuit 39 a. Further, the input buffer 37 of the input circuit 33 cdecides the signal level of the row address strobe signal /RAS suppliedthrough the pad 31 c, converts the row address strobe signal /RAS intoan internal signal RASX of high level or low level, and outputs theinternal signal RASX to the delay circuit 39 b. Still further, the inputbuffer 37 of the input circuit 33 d decides the signal level of thecolumn address strobe signal /CAS supplied through the pad 31 d,converts the column address strobe signal /CAS into an internal signalCASX of high level or low level, and outputs the internal signal CASX tothe delay circuit 39 c.

[0060] The delay circuits 39 a, 39 b, 39 c delay the internal signalsCSX, RASX, CASX for predetermined time periods and output the delayedsignals to the accepting circuits (41 in FIG. 8) as delay signals CS1X,RAS1X, CAS1X, respectively. In the figure, the sizes of the delaycircuits 39 a, 39 b, 39 c express the delay times. The delay times aredetermined in accordance with the lengths of wiring patterns by whichthe respective delay signals CS1X, RAS1X, CAS1X are transmitted to acommand decoder 45 to be explained later. Specifically, the delay timesof each delay circuits 39 a, 39 b, 39 c are set so as to equalize all ofthe totals as follows; (1) the total delay time of the delay signalCS1X, due to the wiring pattern, and of the delay circuit 39 a, (2) thetotal delay time of the delay signal RAS1X, due to the wiring pattern,and of the delay circuit 39 b, and (3) the total delay time of the delaysignal CAS1X, due to the wiring pattern, and of the delay circuit 39 c.Simultaneously, the delay times of each delay circuits 39 a, 39 b, 39 care set so that the set-up times tS and the hold times tH of the signalswhich are accepted by latches to be explained later can besatisfactorily ensured. In this embodiment, the length of the wiringpattern laid to the command decoder 45 is the longest for the delaysignal CS1X and the shortest for the delay signal CAS1X.

[0061] The accepting unit 29 includes the latches 41 a, 41 b, 41 c whichreceive the delay signals CS1X, RAS1X, CAS1X, respectively, and acommand accepting circuit 43 which receives all of these delay signalsCS1X, RAS1X, CAS1X. The latches 41 a, 41 b, 41 c and the commandaccepting circuit 43 correspond to the receiver circuits (41, 43 in FIG.8).

[0062] The latch 41 a receives the internal clock signal CLKIN and thedelay signal CS1X, and outputs internal signals CS2Z, CS2X to thecontrolling unit 23. Further, the latch 41 b receives the internal clocksignal CLKIN and the delay signal RAS1X, and it outputs internal signalsRAS2Z, RAS2X to the controlling unit 23. Still further, the latch 41 creceives the internal clock signal CLKIN and the delay signal CAS1X, andit outputs internal signals CAS2Z, CAS2X to the controlling unit 23.Incidentally, the signals whose symbols end in “Z” are ones of positivelogic, and the signals whose symbols end in “X” are ones of negativelogic.

[0063] The command accepting circuit 43 includes the command decoder 45and a command latch 46. The command latch 46 is the same circuit as eachof the latches 41 a, 41 b, 41 c. This command latch 46 corresponds tothe command signal accepting circuit (46 in FIG. 8).

[0064] The command decoder 45 receives the delay signals CS1X, RAS1X,CAS1X, and outputs a command signal CMD. The command latch 46 receivesthe internal clock signal CLKIN and the command signal CMD, and outputscommand signals CMDZ, CMDX to the controlling unit 23. By the way, thelatches 41 a, 41 b, 41 c and the command accepting circuit 43 arearranged at near positions within the accepting unit 29.

[0065]FIG. 11 shows the details of the clock buffer 35. The clock buffer35 is so constructed that two CMOS inverters 47, 49, and an inverter row51 consisting of two inverters are connected in cascade.

[0066] The source of a pMOS (p-channel MOSFET) 47 b in the CMOS inverter47 is connected to a power supply VCC through a pMOS 47 a. The gate ofthe pMOS 47 a is connected to the ground VSS. In addition, the source ofan nMOS (n-channel MOSFET) 47 c in the CMOS inverter 47 is connected tothe ground VSS through an nMOS 47 d. The gate of the nMOS 47 d isconnected to the power supply VCC.

[0067] The drain of an nMOS 49 c in the CMOS inverter 49 is connected tothe output node of this inverter through an nMOS 49 b. The gate of thenMOS 49 b is connected to the power supply VCC. The output node of theCMOS inverter 49 is connected to the inverter row 51, which outputs theinternal clock signal CLKIN.

[0068]FIG. 12 shows the details of each input buffer 37. The inputbuffer 37 is configured of two CMOS inverters 53, 55 connected incascade, an inverter row 57 consisting of two inverters, and acontrolling circuit 59 for inactivating this input buffer 37. The inputbuffer 37 receives the one of the chip select signal ICS, row addressstrobe signal /RAS and column address strobe signal /CAS by means of theCMOS inverter 53, and it outputs one of the internal signals CSX, RASX,CASX from the CMOS inverter 55.

[0069] The CMOS inverter 53 is the same as the CMOS inverter 47 of theclock buffer 35 shown in FIG. 11, except that the output node of theinverter row 57 is connected to the gate of an nMOS 53 a located on theside of the ground VSS. The CMOS inverter 55 is the same as the CMOSinverter 49 of the clock buffer 35. The input node of the inverter row57 is supplied with an input activation signal ENZ. The input activationsignal ENZ is a signal which becomes a high level during the normaloperation of the SDRAM, and which becomes a low level in the low powerconsumption mode thereof.

[0070] The controlling circuit 59 is configured of three pMOSs 59 a, 59b, 59 c, two nMOSs 59 d, 59 e, and an inverter 59 f. The drain of thepMOS 59 a is connected to the output node of the CMOS inverter 53, andthe source thereof to the power supply VCC. In addition, the gate of thepMOS 59 a is connected to the gate of the PMOS 59 b and the drain of thePMOS 59 c. The sources of the pMOSs 59 b, 59 c are connected to thepower supply VCC. Besides, the gate of the PMOS 59 c is connected to thedrain of the pMOS 59 b. Further, the drains of the pMOSs 59 b, 59 c arerespectively connected to the drains of the nMOSs 59 d, 59 e. Thesources of the nMOSs 59 d, 59 e are connected to the ground VSS. Theoutput node of the inverter row 57 is connected to the gate of the nMOS59 d. Also, the output node of the inverter row 57 is connected to thegate of the nMOS 59 e through the inverter 59 f. The controlling circuit59 has the function of applying the high level to the input of the CMOSinverter 55 through the pMOS 59 a when the input activation signal ENZis at the low level.

[0071]FIG. 13 shows the details of the delay circuits 39 a, 39 b, 39 c.

[0072] Each of the delay circuits 39 a, 39 b, 39 c is a circuit in whicha plurality of inverters 61 a, 61 b, 61 c, 61 d, 61 e are connected incascade through resistors R1, R2 and switches S1-S10. The resistors R1,R2 are formed of diffusion resistances, wire resistances of polysilicon,or the likes.

[0073] In the delay circuit 39 a, the output node of the inverter 61 ais connected to the input node of the inverter 61 b through the resistorR1. Next, the output node of the inverter 61 b is connected to the inputnode of the inverter 61 c through the switch S1. Subsequently, theoutput node of the inverter 61 c is connected to the input node of theinverter 61 d through the resistor R2. Finally, the output node of theinverter 61 d is connected through the switch S2 to the input node ofthe inverter row 61 e in which two inverters are connected in cascade.The inverter row 61 e outputs the delay signal CS1X. The output node ofthe inverter 61 b is also connected to the input node of the inverterrow 61 e through the switch S3. Further, the input node of the inverter61 c is connected to the ground VSS through the switch S4. Stillfurther, a capacitor part 62 a is connected to the input node of theinverter 61 b through the switch S5. Likewise, a capacitor part 62 b isconnected to the input node of the inverter 61 d through the switch S6.Herein, the capacitor part 62 a is configured of MOS capacitors C1, C2,in each of which the source and drain of an nMOS are connected to theground VSS, and the switches S7, S8. On the other hand, the capacitorpart 62 b is configured of MOS capacitors C3, C4 and the switches S9,S10. The gate of the MOS capacitor C1 is connected to the ground VSSthrough the switch S7. Moreover, the gates of the MOS capacitors C1, C2are interconnected through the switch S8. Likewise, the gate of the MOScapacitor C3 is connected to the ground VSS through the switch S9.Moreover, the gates of the MOS capacitors C3, C4 are interconnectedthrough the switch S10.

[0074] Modifying the wiring pattern of a wiring mask for the uppermostlayer makes it possible to turn ON or OFF each of the switches S1-S10.Each of the delay circuits 39 b, 39 c is the same circuit as the delaycircuit 39 a except the ON and OFF states of the switches S1-S10. Inthis embodiment, in the delay circuit 39 a, the switches S1, S2, S5, S6are turned OFF, and the switches S3, S4, S7, S8, S9, S10 are turned ON.Also, in the delay circuit 39 b, the switches S1, S2, S6, S7 are turnedOFF, and the switches S3, S4, S5, S8, S9, S10 are turned ON. Besides, inthe delay circuit 39 c, the switches S3, S4, S7, S9 are turned OFF, andthe switches S1, S2, S5, S6, S8, S10 are turned ON.

[0075] That is, in the delay circuit 39 a, neither of the capacitorparts 62 a, 62 b is connected to the transmission path of the internalsignal CSX. In the delay circuit 39 b, only the capacitor part 62 a isconnected to the transmission path of the internal signal RASX. In thedelay circuit 39 c, both the capacitor parts 62 a, 62 b are connected tothe transmission path of the internal signal CASX. As a result, thedelay times are in the relationship of (delay circuit 39 a)<(delaycircuit 39 b)<(delay circuit 39 c).

[0076] Incidentally, the delay circuits 39 a, 39 b, 39 c can set, atmost, 18 sorts of delay times in accordance with the ON and OFF statesof the switches S1-S10.

[0077]FIG. 14 shows the details of each of the latches 41 a, 41 b, 41 cand command latch 46.

[0078] Each of the latches 41 a, 41 b, 41 c and command latch 46 isconfigured of a signal accepting unit 63 and a signal outputting unit65.

[0079] In the signal accepting unit 63, there are symmetrically arrangeda latching unit 67 in which a pMOS 67 a and nMOSs 67 b, 67 c areconnected in series, and a latching unit 69 in which a PMOS 69 a andnMOSs 69 b, 69 c are connected in series. An accepted signal INZ isoutput from the drains of the pMOS 67 a and nMOS 67 b. An acceptedsignal INX is supplied to the gates of the PMOS 67 a and nMOS 67 b.Likewise, the accepted signal INX is output from the drains of the PMOS69 a and nMOS 69 b. The accepted signal INZ is supplied to the gates ofthe pMOS 69 a and nMOS 69 b. The sources of the pMOSs 67 a, 69 a areconnected to the power supply VCC. Further, the drains of pMOSs 63 a, 63b, the sources of which are connected to those of the pMOSs 67 a, 69 a,are connected to the drains of the pMOSs 67 a, 69 a, respectively. Stillfurther, the output nodes of the inverters 65 a, 65 b of the signaloutputting unit 65 to be explained later are connected to the gates ofthe nMOSs 67 c, 69 c, respectively.

[0080] The internal clock signal CLKIN is supplied to the gates of thepMOSs 63 a, 63 b and an nMOS 63 f. The drains of nMOSs 63 c, 63 d, thesources of which are connected to the ground VSS through the nMOS 63 f,are connected to the drains of the nMOSs 67 c, 69 c, respectively. Anyof the delay signals CS1X, RAS1X, CAS and command signal CMD is suppliedto the gate of the nMOS 63 c. Also, any of the delay signals CS1X,RAS1X, CAS1X and command signal CMD as inverted by an inverter 63 e issupplied to the gate of the nMOS 63 d. The sources of the nMOSs 67 c, 69c are connected to the ground VSS through the nMOS 63 f.

[0081] The signal accepting unit 63 has the functions of receiving therising edge of the internal clock signal CLKIN and activating thelatching units 67, 69, accepting any of the delay signals CS1X, RAS1X,CAS1X and command signal CMD to output the accepted signals INX, INZ tothe signal outputting unit 65.

[0082] The signal outputting unit 65 is configured of an outputtingcircuit 71 which consists of a pMOS 71 a and an nMOS 71 b, an outputtingcircuit 73 which consists of a PMOS 73 a and an nMOS 73 b, the inverters65 a and 65 b, inverters 65 c and 65 d whose input nodes and outputnodes are connected to each other, and inverters 65 e and 65 f. Thegates of the pMOSs 71 a, 73 a are supplied with the accepted signalsINZ, INX, respectively. The sources of the pMOSs 71 a, 73 a areconnected to the power supply VCC. In addition, the output nodes of theinverters 65 b, 65 a are connected to the gates of the nMOSs 71 b, 73 b,respectively. Besides, the sources of the nMOSs 71 b, 73 b are connectedto the ground VSS. The output node of the outputting circuit 71 isconnected to the input nodes of the inverters 65 c, 65 e. On the otherhand, the output node of the outputting circuit 73 is connected to theinput nodes of the inverters 65 d, 65 f. Thus, any of the internalsignals CS2Z, RAS2Z, CAS2Z and the command signal CMDZ is output fromthe inverter 65 e. Also, any of the internal signals CS2X, RAS2X, CAS2Xand the command signal CMDX is output from the inverter 65 f.

[0083] The signal outputting unit 65 has the functions of receiving theaccepted signals INX, INZ in the outputting circuits 71, 73 and latchingthem in the inverters 65 c, 65 d, and then outputting any of theinternal signals CS2Z, RAS2Z, CAS2Z corresponding to the above acceptedsignals and the command signal CMDZ and any of the internal signalsCS2X, RAS2X, CAS2X corresponding to the above accepted signals and thecommand signal CMDX.

[0084]FIG. 15 shows the details of the command decoder 45. The commanddecoder 45 is configured of inverters 45 a, 45 b and a 3-input ANDcircuit 45 c. The inverter 45 a is supplied with the delay signal CS1X.The inverter 45 b is supplied with the delay signal RAS1X. The inputnodes of the AND circuit 45 c are supplied with the outputs of theinverters 45 a, 45 b and the delay signal CAS1X. The AND circuit 45 coutputs the command signal CMD. In this embodiment, the command decoder45 brings the command signal CMD to the high level when the chip selectsignal /CS, row address strobe signal /RAS and column address strobesignal /CAS supplied to the input interfacing unit (21 in FIG. 9) havethe low level, low level and high level, respectively. Thus, the commandlatch 46 shown in FIG. 14 operates to latch the command signal CMD andto output the command signals CMDZ, CMDX to the controlling unit 23(refer also to FIG. 10). Then, the controlling unit 23 executes apredetermined command input process.

[0085] In the SDRAM described above, the input interfacing unit 21accepts the signals supplied from exterior and outputs the acceptedsignals to the controlling unit 23 as will be explained below.

[0086] The chip select signal /CS, row address strobe signal /RAS andcolumn address strobe signal /CAS supplied from exterior are convertedinto the internal signals CSX, RASX and CASX by the input buffers 37 ofthe input circuits 33 b, 33 c and 33 d shown in FIG. 10, respectively.The internal signals CSX, RASX and CASX are respectively supplied to thedelay circuits 39 a, 39 b and 39 c. Subsequently, the delay signalsCS1X, RAS1X and CAS1X obtained by delaying the internal signals CSX,RASX and CASX the predetermined time periods are output from the delaycircuits 39 a, 39 b and 39 c. As shown in FIG. 13, the delay times ofthe respective delay circuits 39 a, 39 b and 39 c can be finely adjustedby the switches S1-S10, and they are adjusted so that the timings ofeach delay signals CS1X, RAS1X and CAS1X arriving at the command decoder45 may coincide. Consequently, the delay signals CS1X, RAS1X and CAS1Xat the input node of the command decoder 45 have the same timings asshown in FIG. 16. Moreover, the set-up time tS and the hold time tH ofthe command signal CMD output from the command decoder 45 shown in FIG.10, with respect to the internal clock signal CLKIN, are equalized. Thatis, the timing margins for the set-up time tS and the hold time tH aremaximized. Thereafter, the command latch 46 outputs the accepted commandsignal CMD to the controlling unit 23 as the command signals CMDZ, CMDX.Since the command signal CMD is generated without the intervention ofany of the latches 41 a, 41 b and 41 c, the output timing thereof isadvanced. It is therefore possible to advance the control timing of thecontrolling unit 23.

[0087] Besides, the delay signals CS1X, RAS1X and CAS1X are supplied tothe latches 41 a, 41 b and 41 c and accepted thereinto at the rise ofthe internal clock signal CLKIN, respectively. The latches 41 a, 41 band 41 c are arranged at positions near the command decoder 45.Therefore, the timing margins of each of the latches 41 a, 41 b and 41 cfor the set-up time tS and the hold time tH with respect to the internalclock signal CLKIN are substantially equalized to the timing margins ofthe command latch 46. To be exact, the timing of each of the delaysignals CS1X, RAS1X and CAS1X shifts in correspondence with the numberof gates (three stages) of the command decoder 45, but the shiftingmagnitude lies within an allowable range. The accepted delay signalsCS1X, RAS1X and CAS1X are respectively output to the controlling unit 23as the internal signals CS2Z as well as CS2X, RAS2Z as well as RAS2X,and CAS2Z as well as CAS2X. Accordingly, the timing margins of theset-up times tS and the hold times tH to the latches 41 a, 41 b and 41 cand the internal clock signal CLKIN of the command latch 46 for aresufficiently given by the delay circuits 39 a, 39 b and 39 crespectively formed in the input circuits 33 b, 33 c and 33 d.

[0088] In the semiconductor integrated circuit constructed as describedabove, the internal signals CS1X, RAS1X and CAS1X delayed thepredetermined time periods by the respective delay circuits 39 a, 39 band 39 c are output to the command decoder 45. Therefore, the timings atwhich the internal signals CS1X, RAS1X and CAS1X arrive at the commanddecoder 45 can be caused to coincide. As a result, the command decoder45 can output the command signal CMD of large pulse width. Accordingly,the command latch 46 can accept the command signal CMD while the set-uptime tS and the hold time tH with respect to the internal clock signalCLKIN are ensured sufficiently.

[0089] The command signal CMD is generated in such a way that theinternal signals CS1X, RAS1X and CAS1X output from the respective delaycircuits 39 a, 39 b and 39 c are directly received by the commanddecoder 45. Therefore, the output timing of the command signal CMD canbe advanced to start the operation of the controlling unit 23 earlier.

[0090] The latches 41 a, 41 b and 41 c and the command accepting circuit43 are arranged at the near positions within the accepting unit 29.Therefore, the timings at which the internal signals CS1X, RAS1X andCAS1X arrive at the respective latches 41 a, 41 b and 41 c and thecommand latch 46 of the command accepting circuit 43 becomesubstantially coincident. In the respective latches 41 a, 41 b and 41 c,accordingly, the timing margins of the internal signals CS1X, RAS1X andCAS1X for the set-up times tS and the hold times tH with respect to theinternal clock signal CLKIN can be substantially equalized to the timingmargins of the command signal CMD in the command latch 46. That is, theacceptance timings of both the latches 41 a, 41 b and 41 c and thecommand latch 46 can be ensured by only the delay circuits 39 a, 39 band 39 c respectively formed in the input circuits 33 b, 33 c and 33 d.

[0091] The input signals (/CS, /RAS and /CAS) received from exterior aretransmitted through the respective delay circuits 39 a, 39 b and 39 c,and the resulting signals are thereafter distributed to the respectivelatch circuits 41 a, 41 b and 41 c and the command accepting circuit 43as the internal signals CS1X, RAS1X and CAS1X. Therefore, the number ofthe delay circuits 39 a, 39 b and 39 c can be minimized. In consequence,the size of the chip can be made smaller.

[0092] The delay time of each of the delay circuits 39 a, 39 b and 39 ccan be modified by changing the transmission path of the signal inaccordance with the ON/OFF states of the switches S1-S10. Therefore, theoptimum delay time can be set for each of the delay circuits 39 a, 39 band 39 c. Even in a case where the adjustment of the delay time hasbecome necessary, the delay time can be modified merely by changing theON/OFF states of the switches S1-S10. Moreover, in case of making thelayout designs of each delay circuits 39 a, 39 b and 39 c, the layoutdata of the elements other than the switches S1-S10 can be made common,so that the layout designing time can be shorten.

[0093]FIG. 17 shows the second embodiment of the semiconductorintegrated circuit according to the present invention.

[0094] In this embodiment, delay circuits 39 a, 39 b, 39 c arerespectively arranged within an accepting unit 29. The remainingconstruction of this embodiment is the same as in the first embodimentdescribed before.

[0095] With this embodiment, effects similar to those of the firstembodiment described before can be attained. Furthermore, since thedelay circuits 39 a, 39 b, 39 c are arranged within the accepting unit29 in this embodiment, they can be located at near positions. As aresult, the connections of the switches S1-S10 can be easily confirmedon a wiring mask by way of example.

[0096] Incidentally, the foregoing embodiments have been exemplified asadjusting the delay times in the way that the switches S1-S10 of thedelay circuits 39 a, 39 b, 39 c are turned ON or OFF by changing thewiring patterns of the wiring masks at the uppermost layer. The presentinvention, however, is not restricted to such an aspect of performance.For example, the delay times may well be adjusted in the way that theswitches S1-S10 are formed of transmission gates made of MOStransistors, and that the transmission gates are controlled to turn ONor OFF. Alternatively, the delay times may well be adjusted in the waythat the switches S1-S10 are formed of fuses made of polysilicon or thelike, and that some of the fuses are blown as are necessary. In the casewhere the switches S1-S10 are formed of the fuses, the blowing of thefuses can be efficiently carried out by arranging the delay circuits 39a, 39 b, 39 c at the near positions as shown in the second embodiment.

[0097] The foregoing embodiments have been exemplified as forming thedelay circuits 39 a, 39 b, 39 c by the use of the resistors R1, R2 andthe MOS capacitors C1, C2, C3, C4. The present invention, however, isnot restricted to such an aspect of performance. For example, each delaycircuit may well be formed by meandering a wiring pattern which has thesame width as that of the wiring pattern of the internal clock signalCLKIN. In this case, the total of the lengths of the wiring pattern ofeach delay circuit and the wiring pattern of, for example, the delaysignal CS1X laid to the latch 41 a is equalized to the length of thewiring pattern of the internal clock signal CLKIN laid to the latch 41a. It is consequently possible to maximize the timing margins of thedelay signal CS1X for the set-up time tS and the hold time tH withrespect to the internal clock signal CLKIN.

[0098] The invention is not limited to the above embodiments and variousmodifications may be made without departing from the spirit and thescope of the invention. Any improvement may be made in part or all ofthe components.

What is claimed is:
 1. A semiconductor integrated circuit comprising adelay circuit which delays an input signal supplied from exterior, and aplurality of receiver circuits which respectively receives a delayedinput signal output from said delay circuit in synchronization with aclock signal.
 2. A semiconductor integrated circuit according to claim1, wherein said delay circuit comprises a switch which changes atransmission path of said input signal and adjusts its delay time.
 3. Asemiconductor integrated circuit comprising: a plurality of delaycircuits which respectively delays input signals supplied from exterior;a plurality of receiver circuits which respectively receives, insynchronization with a clock signal, each of said delayed input signalsoutput from each of said delay circuits; and a logical operating circuitwhich receives more than one of said delayed input signals output fromsaid delay circuits and performs a logic operation.
 4. A semiconductorintegrated circuit according to claim 3, wherein said logical operatingcircuit is a command decoder which outputs a command signal to controlan operation of an internal circuit, and wherein the semiconductorintegrated circuit comprises a command signal receiver circuit whichrespectively receives, in synchronization with said clock signal, saidcommand signal output from said command decoder.
 5. A semiconductorintegrated circuit according to claim 3, wherein said delay circuitcomprises a switch which changes a transmission path of said inputsignal and adjusts its delay time, and said delay time of said eachdelay circuit is respectively adjusted so that the supply timings tosaid logical operating circuit are equal between each said input signal.6. A semiconductor integrated circuit comprising: a plurality of padsfor receiving control signals respectively; a plurality of commanddecoders; and a delay circuit, disposed commonly to said plurality ofcommand decoders, and coupled between said plurality of pads and saidplurality of command decoders, for adjusting the timing of said controlsignals, wherein said plurality of command decoders receive and decodeoutput signals from said delay circuit to output command signals.
 7. Asemiconductor integrated circuit according to claim 6, furthercomprising command latch circuits for latching said command signals inresponse to a clock signal.
 8. A semiconductor integrated circuitaccording to claim 6, wherein a plurality of connection lines betweensaid plurality of pads and said delay circuits have lengths differentfrom each other.
 9. A semiconductor integrated circuit according toclaim 6, wherein said output signals from said delay circuit areoutputted at substantially the same timing.
 10. A semiconductorintegrated circuit circuit according to claim 6, wherein said delaycircuit has a plurality of delay units corresponding to said pluralityof pads, and delay time of said delay units are different from eachother.